This invention relates in general to clock distribution circuits and, in particular, to a new topology of clock distribution wherein clock skew is minimized and other delay line circuits.
Clock signals are repetitive digital pulses, usually derived from a crystal oscillator, with a constant period of repetition or frequency. Clock signals are used in digital systems to synchronize operations between groups of digital gates, time events, and to control the buffering of data and control signals. Due to the large number of digital elements which require clocks in a typical digital system, there are usually multiple copies of the clock signals. These multiple copies of the clocks are produced and distributed by the clock distribution network. The clock distribution network is usually composed of wires, printed circuit board traces, and integrated circuit (IC) buffers. It is very important that the copies of the clock signals be distributed so that all receivers of the clocks receive them at the same time. The differences in arrival time of the various copies of the clock signals are referred to as clock skew. In general, the greater the amount of clock skew, measured in nanoseconds or picoseconds, the greater the loss of system bandwidth and reduction in system operations per second.
Traditionally, clock skew has been controlled by careful measurement and adjustment of the clock distribution network. Wires and PC board traces have been manually adjusted to specific lengths and specially graded integrated circuits used to insure close alignment of the clocks. This was necessary because all integrated circuits have significant variations in propagation delay from IC to IC due to intrinsic semiconductor manufacturing process variations. While a single IC can provide a small number of clocks with very low skew, a clock distribution network composed of more than one IC will have significant skew due to the variation between ICs.
More recently, clock distribution ICs have been developed which use active compensation techniques to automatically adjust for this intrinsic semiconductor process variation. These ICs are based on the use of the phase lock loop (PLL) method. The PLL contains an internal oscillator which is adjusted until its frequency, or a subdivision, of oscillation matches that of an external input reference clock signal. The oscillator output also drives some number of the IC outputs. The practical effect is that the PLL ICs appear to have zero propagation delay since the output clock signals appear almost at the same time as the input reference clock signal. Since the PLL clock distribution IC appears to have zero propagation delay, the task of producing a precise clock distribution network is greatly simplified. As long as all wires and PC board traces in the network are matched, the zero delay PLL ICs will not contribute any variations to the resultant multiple clock copies. Thus, multiple clock copies with low skew can be produced.
However, PLL clock distribution ICs suffer from a number of limitations which prevent the above ideal scenario from being achieved. PLL ICs have the fundamental problem of trying to distribute clocks by independently generating new clocks and then trying to adjust all of the new clocks to the desired reference clock. This integrated circuit design approach has two requirements: generating a new clock and adjusting the new clock to the reference clock.
The first requirement of generating a stable, low noise and high frequency clock in an integrated circuit is difficult. The use of precise high frequency, typically 300 to 800 MHz, analog oscillator circuits is necessary. This requires a semiconductor process which is capable of producing precise high frequency analog circuits. Compounding the difficulties is the vulnerability to noise by analog circuits. Analog circuits are much more vulnerable to noise compared to digital circuits due to uniform linear response instead of digital's binary threshold response to noise. Stable low noise oscillators typically will work only over a limited range of frequencies.
The second requirement of adjusting this sensitive high frequency analog oscillator to the desired reference clock is also very difficult. The adjustment circuits are typically composed of a phase detector to measure the mismatch between the newly generated clock and the desired reference clock and a filtered charge pump to control the internal oscillator. The phase detector outputs two pulses, the widths of which are used to control the charge pump. The charge pump is ideally a precise symmetrical analog circuit which provides a uniform linear amount of current to the oscillator in response to the widths of the two control pulses. Again, the demands of the precision analog circuits are hard to meet.
Additional problems with PLL ICs include high power consumption due to the high frequency internal oscillator, inability to handle sudden change in clock frequency, lack of control over duty cycle, and difficulty in layout on a printed circuit board.
It is therefore desirable to provide an improved clock distribution circuit whereby the above-described difficulties are not present.